QSPI Fundamentals

[中文]

Overview

QSPI operates as a master to communicate with generic slave devices such as flash, PSRAM, or displays. It supports single-, dual-, and quad-data-line SPI transfers and works in two modes:

  • Indirect mode: all operations are issued through QSPI registers.

  • Memory-mapped mode: the external device is mapped into the MCU’s address space so the system treats it like on-chip memory.

Key features:

  • Two operating modes: indirect and memory-mapped

  • Fully programmable opcodes and frame formats

  • Integrated TX and RX FIFOs

  • Interrupts on transfer completion

QSPI ↔ Device Transaction Stages

A typical transaction consists of the CMD, ADDR, WAIT, and DATA phases.

CMD phase

Commands are normally sent on a single data line, but dual/quad width is also supported via registers. Most devices (flash, PSRAM, OLED) use single-line commands. Up to 8 bytes are stored in CMD registers, which describe not only opcodes but also address bytes when required. There are four predefined command registers (CMDA–CMDD); each SPI operation selects one of them.

  • CMDA: memory-mapped writes

  • CMDB: memory-mapped reads

  • CMDC: indirect writes via TX FIFO

  • CMDD: indirect reads via RX FIFO

For memory-mapped mode you configure CMDA/B once; subsequent reads/writes reuse the configuration. In indirect mode each FIFO operation or device command must enable the corresponding CMD register. Choose the mode according to the peripheral: PSRAM typically uses memory mapping, while flash generally uses indirect mode.

ADDR phase

Addresses can be transmitted on 1/2/4 data lines and typically span 3–4 bytes. CMDA–CMDD offer flexible configuration. In memory-mapped mode (CMDA/B) the hardware auto-generates addresses. In indirect mode (CMDC/D) software defines which bytes are opcodes, addresses, or dummy cycles, as well as their bus widths. The hardware cannot infer address locations automatically. In direct-mapped mode the address comes straight from the bus (base 0x6800_0000 corresponds to device address 0).

WAIT phase

Idle cycles inserted between command bytes. The number of dummy cycles is configured by DUMMY_CLK and their position by DUMMY_MODE. For example, CMD1 may be opcode, CMD2–4 addresses, and dummy cycles inserted after CMD4 to meet device timing requirements. FIFO handles the actual data transfer.

DATA phase

Transfers data on the configured bus width. FIFO depth is 256 bytes. DATA_LINE sets the line width and DATA_LEN sets the transfer length. Indirect mode uses TX/RX FIFOs, while memory-mapped mode reads/writes directly through the system bus.